1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to avoiding timing and congestion problems in register transfer level (RTL) code for multiplex structures in an integrated circuit design.
2. Description of the Prior Art
Complex multiplex structures are one of the main causes of congestion problems in the layout of field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs. In previous methods of checking for congestion problems, a netlist is generated from the register transfer level (RTL) code for the integrated circuit design by a layout tool to determine whether the netlist is routable. If not, then the RTL code is modified to relieve routing congestion and a new netlist is generated and checked, and so on, until a routable netlist is generated.